In general, non-volatile memory devices can store data even when power is not provided. A flash memory may electrically erase data of cells at a time. Thus, the flash memory has been widely used in computers and memory cards.
The flash memory includes two types of memory: a NOR-type flash memory and a NAND-type flash memory. In the NOR-type flash memory, two or more cell transistors are connected to a bit line in parallel. In the NAND-type flash memory, two or more cell transistors are connected to a bit line in series. The NOR-type flash memory stores data using a channel hot electron method and erases the data using Fowler-Nordheim tunneling (F-N tunneling) method. The NAND-type flash memory stores and erases data using F-N tunneling method. Generally, the NOR-type flash memory may be unsuitable for highly integrated semiconductor devices due to high power consumption of the NOR-type flash memory. Thus, even though the NOR-type flash memory can access with high-speed easily, the NAND-type flash memory consuming smaller cell current as compared to the NOR-type flash memory device is preferred in highly integrated semiconductor devices.
FIG. 1 is a block diagram showing a structure of a conventional NAND-type flash memory 100 disclosed in U.S. Pat. No. 6,288,936 with reference numerals added for the convenience of explanation.
Referring to FIG. 1, the NAND-type flash memory 100 includes a NAND-type memory cell array 110 in which a plurality of cell transistors are connected to one bit line in series. First and second page buffers 122 and 124 are connected to top and bottom of the memory cell array 110 respectively. A page buffer control unit 130 controls an operation of the first and the second page buffers 122 and 124. A main control unit 140 controls operations of the NAND-type flash memory 100. An Input-Output (I/O) Buffer 150 stores input/output data of each of the first and the second page buffers 122 and 124.
The first page buffer 122 is connected to even-numbered bit lines (BL0, BL2, BL4, . . . ) of the memory cell array 110. The second page buffer 124 is connected to odd-numbered bit lines (BL1, BL3, BL5, . . . ).
The page buffer control unit 130 generates control signals under a control of the main control unit 140. The first and the second page buffers 122 and 124 transmit program data to the memory cell array 110 in response to control signals generated from the buffer control unit 130. The first and the second page buffers 122 and 124 also read data from the memory cell array 110. For instance, if data is read from the flash memory, the read data of pertinent page is transferred from the memory cell array 110 to the first and the second page buffers 122 and 124. Then the data is outputted as 1 Byte (8 bits) to the I/O buffer 150 according to an address of a column. Generally, a program or read operation of this NAND-type flash memory is performed by a page unit. An erase operation of the programmed data is performed in a block unit assembled with several pages. For example, in a 32 Mb flash memory, one page is configured with 512 B+16 B (a spare region), and one block is configured with 32 pages. Thus, the 32 Mb flash memory is made with 2,048 blocks.
In the flash memory 100 shown in FIG. 1, a plurality of control signals 10 are sent/received between the page buffer unit 130, and the first and the second page buffers 122 and 124. The page buffers 122 and 124 are disposed in top and bottom of the memory cell array 110. Data 20 is also sent/received between the first and the second page buffers 122 and 124, and the IO buffer 150. A plurality of signal lines for sending/receiving a plurality of control signals and/or data are disposed among the first and the second page buffers 122 and 124, the page buffer control unit 130 and the I/O buffer 150. Generally, in conventional technology, control logics such as the page buffer control unit 130 and the I/O buffer 150 are located under the memory cell array 110 in the flash memory 100. However, as shown in FIG. 1, when the page buffers 122 and 124 are located top and bottom of the memory cell array 110, respectively, it is preferable to have a plurality of control signals to be transmitted to the page buffers 122 and 124 to be provided from a peripheral logic located under the memory cell array 110.
In FIG. 1, a plurality of signal lines 10 connected to the first and the second page buffers 122 and 124 are arranged by partially assigning an edge region of a flash memory chip 100. An occupying area of signal lines on the chip is determined depending on the width and specification of signal lines. The conventional arrangement of this signal lines may increase a chip size of the flash memory 100 because additional regions need to be assigned on the flash memory chip for signal lines. Furthermore, since the length of an interconnection connected to the respective page buffer may be different, a skew may occur. Thus, predictions for signal transformations may be difficult.
For arranging the signal lines on the flash memory chip in different manner, the control logic (e.g., the page buffer unit 130 or the I/O buffer 150) may be set at center of the chip. However, the flash memory chip size may also increase because an additional region on the flash memory chip for arranging the signal lines is needed. In addition, it may be difficult to embody cut-down version used by a memory capacitance because the control logic is located at the center of the flash memory chip.